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The work presents a configurable network interface (NI) macrocell to be integrated in Spidergon network-on-chip (NoC) infrastructures, and addresses the problem of its functional verification. The NI architecture supports multiple native bus for the IP cells connected to the NoC and the conversion of data size, protocol and frequency between the NoC and each IP. Differently from many state-of-art...
Functional verification plays an important role in the design flow of an intellectual property (IP) core and, in general, of an embedded system. The industrial trend of the last two decades has been to produce more and more complex embedded systems by integrating several IP cores on a single chip die; while this is easily possible thanks to the availability of ready-to-use off-the-shelf components,...
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