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This paper presents a novel low power duobinary voltage mode transmitter in 90-nm CMOS process for wireline communication. As a matter of fact, voltage mode transmitters potentially save much more power than current mode transmitters. By adding a medium level, a half supply voltage, to conventional NRZ voltage mode transmitters, duobinary coding can simply be achieved. Post-layout simulation demonstrates...
This paper presents a dual-edge sampling clock-embedded signaling (CES) DLL based CDR. By combining the proposed dual edge sampling and half-UI embedded clock coding, the proposed method can save 4 times number of the required delay cells compared to the conventional DLL, enhancing the power efficiency and reducing silicon area. The test chip is designed in TSMC 180-nm CMOS process. The core area...
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