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Recently, we proposed a low-granularity back-bias control technique [1] optimized for the ultra-thin body and box (UTBB) fully-depleted silicon-on-insulator (FD-SOI) technology. The technique was preliminary evaluated through the design of a low-voltage 8-bit ripple carry adder (RCA), showing very competitive energy and delay values. In this paper, the characteristics of the low-granularity back-biasing...
Dynamic gate-level body biasing has been recently proposed as an alternative design methodology for subthreshold logic gates. According to this approach, a simple body biasing circuit, embedded in the logic gate, is exploited to change dynamically the threshold voltage of transistors on the basis of the gate status. This allows fast gate switching, while maintaining high energy efficiency. In this...
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