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3D-ICs based on TSV technology provide high bandwidth inter-chip connections. The drawback is that most of the existing TSVs consume a large amount of silicon real estate. We present circuit-level design and analysis of area efficient, low power, high-data-rate 3D serial TSV links. A design space exploration is performed and trade-offs in terms of area, power and performance are presented. Circuit...
An asynchronous 8× interleaved redundant SAR ADC achieving 8.8GS/s at 35mWand 1V supply is presented. The ADC features pass-gate selection clocking scheme for time-skew minimization and per-channel gain control based on low-power reference voltage buffers. The sub-ADC stacks the capacitive SAR DAC (CDAC) with the reference capacitor to reduce the area and enhance the settling speed. It achieves 38...
We have designed and fabricated double-gate ambipolar field-effect transistors, which exhibit p-type and n-type characteristics by controlling the polarity of the second gate. In this work, we present an approach for designing an efficient regular layout, called Sea-of-Tiles (SoTs). First, we address gate-level routing congestion by proposing compact layout techniques and novel symbolic-layout styles...
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