The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
We will present the strip readout prototype for ATLAS small-strip Thin Gap Chamber(sTGC) Phase-I Muon trigger upgrade, which named strip Front End Board(sFEB). The prototype includes 8 VMM2 ASICs for strip signal conditioning, a Xilinx Kintex-7 FPGA for VMM2 configuration and events readout, a commercial ethernet chip working at the physical layer. The sFEB prototype is described in details.
The ATLAS detector will be upgraded in 2018. The main focus of the Phase-I ATLAS upgrade is on the Level-1 trigger, replacing the present muon small wheels (SW) with the “new small wheel(NSW)”, which consists of small thin gap chamber(sTGC) and micromegas (MM). A versatile application-specific integrated circuit(ASIC), the VMM chip, have been developed to read out the signals of the sTGC and MM. The...
We design a Data Acquisition (DAQ) system for a 10-Gbps true random number generator to verify the quality of the random number. The prototype of the DAQ is based on a Xilinx Vertex-6 FPGA evaluation board. The DAQ system has three parts: acquisition, cache, and data up-link. Acquisition is the interface to the high-speed random data, and we use Gigabit Transceiver (GTX) in FPGA to deserialize the...
We will present a DAQ prototype designed for the ATLAS small-strip Thin Gap Chamber (sTGC) Phase-I trigger upgrade. The prototype includes two VMM2 chips developed to read out the signals of the sTGC, a Xilinx Kintex-7 FPGA used for the VMM2 configuration and the events storage, and a Gigabit Ethernet Transceiver (GET) working at the physical layer. The features of the DAQ prototype are described...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.