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In this work, we have done power analysis of Data Encryption Standard (DES) algorithm using Xilinx ISE software development kit. We have analyzed the amount of power utilized by selective components on board i.e., FPGA Artix-7, where DES algorithm is implemented. The components taken into consideration are clock power, logic power, signals power, IOs power, leakage power and supply power (dynamic...
In Text analysis, the current focus of researcher is on performance. There is a wide research gap to design energy efficient hardware which is in use in text analysis. When room temperature is 25 degree Celsius, there is 60.01%, 39.98%, 20% reduction in Clock Power when we scale down device operating frequency from 250GHz to 200GHz, 150GHz and 100GHz respectively. When ambient temperature is 50 degree...
In this paper, we study the effect of using digitally controlled impedance IO Standard in memory interface design in terms of power consumption. In this work, we achieved 50% dynamic power reduction at 1.5V output driver voltage, 35.2% dynamic power reduction at 1.8V output driver voltage in comparison to 2.5V output driver voltage in DCI based IO standard implementation on input or output port in...
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