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In this paper, we have tried to make energy efficient ALU on 90nm based Virtex-4 FPGA using different I/O standards, as with the scaling of technology power dissipation has become a major concern for high performance ALU design. As 50% of the total power of ALU is dissipated only in clock and I/O pads, hence in order to make it energy efficient clock gating technique is introduced and the analysis...
Power is directly proportional to voltage. In this work, voltage scaling is applied in design of low power Vedic multiplier. There is 86–98% saving in leakage power and 4–9% saving in IOs power, when we scale down voltage from 1.5V to 0.5V. Vedic multiplier has now proven its supremacy on traditional multiplier in terms of performance, speed or delay. There is no research work is going on in energy...
This design is implemented on 90nm Virtex (4xc4vfx12), 65nm Virtex 5(xc5vlx20t2ff323), and 40nm Virtex 6(xc6vcx75t). I/O power is the major contributor in dynamic power dissipation in VLSI design. In this work, different I/O standard of HSTL (High Speed Transceiver Logic) is taken under consideration in order to find the most energy efficient I/O standard from I/O power perspective. I/O power is the...
In this work of low power memory design on FPGA, we are using the most energy efficient I/O standard among LVCMOS, HSLVDCI, HSTL, LVDCI_DV2 and SSTL. I/O standard is used to match impedance of transmission line, impedance of port and impedance of memory for avoidance of transmission line reflection. In naming convention of I/O Standard, LV is Low Voltage, HS is High Speed, DV2 is Half Impedance, CMOS...
In this work, we are making 802.11 WLAN Channel specific energy efficient ALU using the HSUL_12 (High Speed Unterminated Logic) IO standard. This ALU design is implemented on FPGA. In this experiment, Xilinx 14.6 is used as simulator, Verilog is used as verification language and XPower is the power consumption estimator. Capacitance scaling technique is used for reduction in IOs power. We scale down...
Punjabi is ranked 1st in languages of Pakistan [5], 11th in Indian languages [6] and 3rd in Indian Subcontinent. In order to write Punjabi: Gurmukhi script is used in India and Shahmukhi in Pakistan. A lot of research is going on in Pakistan and India in the domain of natural language processing but, no research group is working especially for Punjabi to design Unicode reader. The Unicode range of...
In this project, we are using LVCMOS and HSTL IO standards in order to match the resistance of input and output line, input and output port and Vedic multiplier. The primary purpose of Impedance matching is to eliminate transmission line reflection. Now, impedance matching is used to increase the stability of device with the help of IO standard. Therefore, selection of energy efficient IO standard...
In this work, we are integrating thermal aware design approach in energy efficient Vedic multiplier on FPGA. In the beginning of this universe, Veda describes heat receiving from the Sun god as Suryamrit (Surya i.e. Sun +Amrit i.e. Nectar= Suryamrit i.e. Nectar coming from the Sun God). Now, whole world is feeling anxious about temperature. How our thinking pattern is changing with evolution of mankind?...
In this work, we designed a power efficient memory circuit using family of various HSTL IO Standards on 28nm Field Programmable Gate Array (FPGA). Nine different HSTL IO Standards are compared with each other to search the most power efficient one. We validated our circuit with different HSTL IO Standards and on Different frequency range to obtain a most power efficient circuit. In our experiment,...
In this work, we are using Stub Series Transistor Logic (SSTL) on the simplest VLSI circuit multiplexer and analyze the power dissipation with different class. Using SSTL15 in place of SSTL2_II_DCI, there is reduction of 304mW power i.e. 76.19% power reduction. Using HSTL_I_12 in place of HSTL_III_DCI_18, there is reduction of 157mW power i.e. 62.3% power reduction. HSTL and SSTL are IO standards...
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