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Power reduction is nowadays becoming the first consideration in VLSI design. Low power is one of major concerns in deeply scaled CMOS technologies. There have been many methods in very wide rang to achieve this objective. And the Register-Transfer level (RTL) has become the most effective stage in low power VLSI design, according to the significant power optimization impact and accurate power estimation...
For ultra-low-power multimedia mobile processor (MMP) design, clock-power reduction is critical because the largest portion of the total power (more than 60% in the processor designs used in this paper) is consumed in the sequential logic. Currently, for the clock-power reduction, traditional combinational clock gating scheme has been used in industry and recently, sequential clock gating method is...
Enable-based Clock Gating (ECG) during synthesis to reduce the pipeline power consumption is widely used in scaled technologies. However, the ECG does not provide optimal solution at all in terms of power because it is synthesized by a global way and it does not consider the correlation between clock-enable signal and data signal. We propose a novel single comparator-based clock gating (SCCG) scheme...
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