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Even though much previous work explores adapting instruction queue (IQ) and reorder buffer (ROB) sizes to application requirements, traditional IQ/ROB optimizations may be prohibitive for resource-constrained embedded systems, due to the hardware/execution time overheads. We propose low overhead, phase-based instruction window optimization to dynamically vary IQ and ROB sizes for different execution...
Partial reconfiguration (PR) enhances traditional FPGA-based reconfigurable embedded systems with benefits such as reduced resource requirements and increased functionality. Since fully realizing these PR benefits requires extensive PR design flow knowledge, as well as the target FPGA's low-level architectural details, PR has not yet gained widespread usage. To alleviate manual design-time effort,...
The cache hierarchy's large contribution to total microprocessor system power makes caches a good optimization candidate. To facilitate a fast design-time cache optimization process, we propose a single-pass trace-driven cache simulation methodology—T-SPaCS—for a two-level exclusive cache hierarchy. Direct adaptation of conventional trace-driven cache simulation to two-level...
Cache tuning is the process of determining the optimal cache configuration given an application's requirements for reducing energy consumption and improving performance. As embedded systems trend towards unified second-level caches for improved performance, the need for fast cache tuning methodologies for multi-level cache hierarchies is becoming more critical. In this paper, we present U-SPaCS, a...
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