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Architecture efficiency, in terms of performance/area, of application-specific processors is directly related to the devised instruction set and pipeline stages usage. Most of recently proposed works on application-specific instruction-set processors (ASIP) do not consider or present this key point explicitly. In this paper, we consider the challenging turbo decoding application where many recent...
In order to address the large variety of channel coding options specified in existing and future digital communication standards, there is an increasing need for flexible solutions. Recently proposed flexible solutions in this context generally presents a significant area overhead and/or throughput reduction compared to dedicated implementations. This is particularly true while adopting an instruction-set...
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