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This paper proposes a QC-LDPC partial parallel architecture that implements a hard decision message passing algorithm based on Gallager-B decoding. The proposed architecture uses an optimized variable node unit, with adaptive threshold, suitable for irregular LDPC codes. We present implementation results for WiMAX rate 1/2 code for FPGA technology. These indicate a cost reduction of 2.5x in logic,...
This paper proposes a dual-clock based solution for QC-LDPC partially parallel flooded decoders. It aims at reducing memory and routing overhead, while maintaining a high degree of parallelism at processing node level. We take advantage of the high memory working frequencies with respect to the processing units, and use two clock domains: a high frequency for memory and the barrel shifter based routing...
Sorting represents one of the most important operations in data center applications. In this paper, we propose a hardware-software FPGA accelerated based solution for very large data set merge sorting. The accelerator is using a FIFO based approach for sorting. The main contributions of the proposed solution are: (i) configurable FIFO buffers in order to address the variable size of the pre-sorted...
Implementation of Quasi-Cyclic (QC) Low Density Parity-Check (LDPC) decoder on FPGA devices has shown great interest in both wireless communication, as well as error correction for Flash memories. This paper presents an FPGA flooded LDPC decoder which uses multiple codeword processing for efficient memory utilization. It is based on a partially parallel implementation, which relies on memory blocks...
This paper presents an automated template-based approach for layered QC-LDPC architectures. The underlying idea is to be able to generate any number of fairly optimized hardware designs with only a minimum effort required by tuning high level parameters (parity check matrix, number of AP-LLR messages being processed at a time, etc.). Having chosen a partially parallel architecture, template design...
This paper addresses the problem of providing support for energy consumption accounting and performance evaluation by means of performance counters in an open source processor core — OpenRISC OR1200. The OpenRISC processing core is flexible in that it allows different hardware configurations, and provides full support on the tool-chain side. In addition to this, it gives full hardware design access,...
Serial based FPGA fault emulation schemes for probabilistic errors rely on a random number generator -- which is used for generation of fault bits - and a shift register - used for placing the fault bits to their corresponding fault location. It has two advantages with respect to parallel solutions: lower cost and better accuracy. The main disadvantage is represented by the high emulation overhead:...
This paper proposes a FPGA implementation based on sliding processing window for Harris corner algorithm. It represents one of the most frequently used pre-processing method, for a wide variety of image processing algorithms, such as feature detection, motion tracking, image registration, etc‥ It relies on a series of sequential steps, each processing an image outputted by the previous step. The purpose...
This paper proposes an FPGA based layered architecture for quasi-cyclic (QC) irregular LDPC decoder. Our approach is based on merging variable and check node processing into one single variable-check node (VCN) unit. Layer message computation is done using a parallel scheme of a number of VCNs equal to the expansion factor of the QC matrix. The proposed architecture is characterized by the serial...
This paper presents a hybrid fix point - floating point (FP) multiplication unit. It has as inputs a fixed point and a FP number and outputs a FP number. Algorithm and corresponding architecture are proposed. Two distinct approaches have been implemented on Xillinx Virtex 5 FPGA board: one geared towards performance whilst the second is optimized for cost. Synthesis results show an improvement up...
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