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This paper addresses the problem of reliability and makespan optimization of hardware task graphs in reconfigurable platforms by applying fault tolerance (FT) techniques to the running tasks based on the exploration of the Pareto set of solutions. In the presented solution, in contrast to the existing approaches in the literature, task graph scheduling, tasks parallelism, reconfiguration delay, and...
This paper presents a novel statistical model to estimate the reliability and number of errors of hardware tasks running on partially reconfigurable FPGAs in harsh environments. The proposed model has been validated by means of fault injection. The obtained results endorsed by the 95% confidence interval reveal the high accuracy of the proposed reliability model.
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