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Continuous technology scaling and increased demand for computational power have introduced a paradigm shift in manycore design requirements. On the other hand, tight power budgets and limitations of voltage scaling are throttling the ability to optimally exploit the potential of these systems, leading researchers to adopt aggressive voltage scaling techniques such as Near-Threshold Computing (NTC)...
A variety of dynamic thermal management (DTM) schemes have been proposed to address the adverse effects of high temperatures on a chip. These DTM schemes rely on on-chip thermal sensors to get accurate temperature information over a die, and typically assume on-chip thermal sensors give accurate temperature readings. However, on-chip thermal sensors with small footprint and low power consumption,...
Recently, numerous techniques have been proposed so that the temperature distribution of a chip can be managed dynamically during its operation, and these dynamic thermal management (DTM) schemes rely on on-chip thermal sensors in order to get the accurate temperature information. The challenging question is how to allocate a proper number of sensors on a die in order to get the accurate thermal information...
In this paper the authors demonstrate the impact of the floorplan on the temperature-dependent leakage power of a system on chip (SoC). We propose a novel system level temperature aware and floorplan aware leakage power estimator, STEFAL, which considers both the floorplan of the SoC and the cycle-by-cycle dynamic power behavior while estimating the leakage power. The authors implemented our estimation...
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