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This paper presents a novel yield model for integrated circuits manufacturing, considering lithography printability problems as a source of yield loss. The use of regular layouts can improve the printability of IC layouts, but it results in a significant area overhead by introducing regularity. To the best of our knowledge, this is the first approach that considers the tradeoff of cells with different...
Leading-edge chip makers are moving towards more regular litho-friendly design styles in order to combat litho-induced process variations. This paper explores layout design providing several layout templates and we propose a fast and simple design metric to evaluate the potential benefits and weaknesses of a given template. We show that a regular cell template can achieve similar overall qualification...
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