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In this paper, we propose a novel sorting algorithm that sorts input data integer elements on-the-fly without any comparison operations between the data—comparison-free sorting. We present a complete hardware structure, associated timing diagrams, and a formal mathematical proof, which show an overall sorting time, in terms of clock cycles, that is linearly proportional to the number of inputs, giving...
The substantial increase in market demand for handheld devices drives the need for low-power high-speed data access SRAM for systems-on-chip (SoCs). In this paper, we present a novel low-power SRAM architectural design that provides high-noise margin double data rate (DDR) read/write accesses using a conventional 8T-Cell and a partitioned architectural structure consisting of even and odd modules...
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