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A major challenge in design space subsetting is the time consumed in evaluating all of the design space configurations and selecting a subset of best/near-best configurations—those that adhere closely to design constraints. If an architect determines a subset for an instruction set architecture (ISA) that is historically coupled the system's domain, the evaluation process must be repeated if the architect...
Due to harsh and inaccessible operating environments, space computing presents many unique challenges with respect to stringent power, reliability, and programmability constraints that limit on-board processing performance and mission capabilities. However, the increasing need for real-time sensor and autonomous processing, coupled with limited communication bandwidth with ground stations, are increasing...
Cache tuning reveals substantial energy savings for single-core architectures, but has yet to be explored for multi-core architectures. In this paper we explore level one (L1) data cache tuning in a heterogeneous dual-core system where each data cache can have a different configuration. We show that L1 data cache tuning in a dual-core system achieves 25% average energy savings, which is comparable...
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