The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
ORB (Oriented FAST and Rotated BRIEF) feature extraction is popular in embedded vision applications like visual navigation due to its higher speed and robustness in many situations. However, feature description in ORB still accesses large amounts of image patches especially when an image pyramid is built. In order to reduce internal memory cost as well as maintain low latency processing, we design...
As one of the mostly used synchronization schemes in parallel programming on multi-core processors, barrier synchronization has been extensively studied in former research works. In conventional master-slave barrier or tree barrier, usually one centric core is selected to collect barrier arriving messages and to broadcast barrier releasing messages. Unfortunately the barrier core sometimes is deviated...
As one of the mostly used synchronization schemes in parallel programming, spin lock is supported in most off-the-shelf multi-/many-core processors. However the classical spin lock synchronization may lead to contention of acquiring the only lock and starvation of some threads busy waiting to be served. Thus queue-based spin lock has been put forwarded to eliminate both contention and unfairness issues...
Parallelized applications running on many-core Network-on-Chip (NoC) processors may consume a great part of execution time to synchronize threads mapped on multiple NoC nodes, if synchronization for NoC processors is not carefully designed. In this paper, we propose an instruction-based synchronization solution applied in a packet-switched many-core NoC processor with 2D mesh grid topology. Return...
Nowadays, the scratchpad memories (SPMs) are widely used as supplements or even alternatives for cache memories in audio applications on cost-effective SoCs. However, traditional SPM architectures encounter limitations of tight capacities and restricted data exchange methods with main memories. Such kinds of limitations significantly decrease the performance of the whole system, since most of the...
In this paper, we present a cache scheme targeting hardware implementation to reduce the bandwidth of motion compensation, and a block-pipelining strategy to hide long latency of the external memory in high definition H.264/AVC video decoder. Hardware architecture is also implemented for the proposed algorithms. Experimental results show that the cache succeeds in reducing external memory bandwidth...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.