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Heterogeneous systems on a single chip composed of a central processing unit, graphics processing unit (GPU), and field-programmable gate array (FPGA) are expected to emerge in the near future. In this context, the system on chip can be dynamically adapted to employ different architectures for execution of data-intensive applications. Motion estimation (ME) is one such task that can be accelerated...
Recently, the parallel processing capability of the Graphics Processing Unit (GPU) has been employed for accelerating motion estimation in H.264/AVC encoder implementations. However, while implementing parallel motion estimation on GPU, the bit rate cost of the motion vector is generally ignored. This is due to the unavailability of the spatially predicted motion vectors, which leads to rate-distortion...
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