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A low power Operational amplifier (Opamp) using Process, temperature insensitive current source has been presented. The design methodology of the addition based current source and the Opamp implementation using this current source is presented. The spice simulations are carried out in GPDK 90 nm technology at 0.6 V supply. The results of addition based current source Opamp are compared with the MOSFET...
Secondary users can utilize the spectrum in the absence of primary users (PU) in cognitive radio networks (CRN). Hence there is a need to sense the spectrum perfectly. Because of hidden node problem, the sensing information given by single SU may not be reliable information. In cooperative spectrum sensing, local sensing is performed by number of SUs and report their local decisions to fusion center...
According to the Launder's principle, in binary for each bit loss information kTln2 of heat is dissipated. All the present designs like CMOS are irreversible logics which losses bit information. Reversible logic is the better way of reducing power consumption. Bit loss always give the more power consumption but here by recovering bit loss using reversible logic we are getting less power consumption,...
This paper proposes the design of a second order sigma delta modulator (SDM) to be used in medical implants for conversion of low frequency human body analog signals into digital format. The lifetime of a medical implant is governed by the power consumed by various blocks in it, of which the block consuming maximum power is the Analog to Digital Converter (ADC). This paper aims at designing a power...
A low voltage and low power Operational amplifier (Opamp) using Process, temperature insensitive current source has been presented. The design methodology of the addition based current source and the Opamp implementation using this current source is presented. The spice simulations are carried out in GPDK 90 nm technology at 0.6 V supply. The results of addition based current source Opamp are compared...
Different approaches for implementing a complex multiplier in pipelined FFT are considered and implemented to find an efficient one in this paper. The design is implemented in VHDL and design is synthesized on FPGA to know the performance. The design is implemented with a focus of reducing the resources used. Some approaches resulted in the reduced number of DSP blocks and others resulted in reduced...
In modern world video compression technology is developed in to a bloomed field, with several techniques available for a wide range of applications like video transmission, HDTV, broadcast digital video. Motion Estimation (ME) is a key component for high quality video compression, which is characterized by its high computation complexity and memory requirements. Motion Estimation has been conventionally...
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