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In comparison with the popular feature algorithms in vision applications, AFFINE-SIFT (ASIFT) achieves the highest robustness in terms of illumination, rotation, and scale in affine space but exhibits high computation complexity. This work proposes three optimization techniques, including reverse based pipelined affine computing, full parallel Gaussian pyramid computing and rotation invariant binary...
Speeded Up Robust Feature(SURF) is widely used in computer vision applications. In many recent applications like mobile devices and vision sensor network, it is extremely difficult to meet both the performance and power consumption requirements of SURF implementations, especially for CPU, GPU, DSP or FPGA based solutions. In this paper, the SURF algorithm is simplified and optimized for hardware implementation...
How to map IP cores onto NoC architectures is a significant issue (application mapping) in multi-core system design. Many mapping algorithms which aim at optimizing cost metrics(e.g. energy consumption) in the mapping procedure are proposed. Some of those algorithms consider satisfying performance metrics (e.g. latency) constraints. This paper analyses the mechanism leading to performance decreases...
Effective fault tolerant techniques are crucial for a Network-on-Chip (NoC) to achieve reliable communication. In this paper, a novel VLSI architecture employing redundant routers is proposed to enhance the fault tolerance of an NoC. The NoC mesh is divided into blocks of 2×2 routers with a spare router placed in the center. The proposed fault-tolerant architecture, referred to as a quad-spare mesh,...
This paper proposes a reconfigurable multi-processor SoC for media applications called REMUS (REconfigurable Multi-media System), which consists of 512 processing engines and two ARMs. The processing engines are divided into two dynamic configuration groups, which can be easily tailored and extended. The processing engines, DBIs (Data Buffering Interface, DBI) and context interfaces build up a large...
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