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A fully integrated low-power 2.4GHz ZigBee transceiver with inductor-less RF front-end implemented in 180nm CMOS technology is demonstrated. The proposed double push-pull LNA collaborates with a current-mode down-converter to provide wideband low-noise reception, as well as the out-of-band blocker resilience. A sliding frequency synthesizer (FS) with low-frequency running VCO is employed to provide...
This paper proposes a wideband subharmonically injection-locked PLL (SILPLL) with adaptive injection timing alignment technique. The SILPLL includes three main circuit blocks: one-oscillator-period constant-delay (OOPCD) divider, timing-adjusted phase detector (TPD), and pulse generator (PG). The proposed injection timing alignment technique can align the injection timing adaptively in a wide range...
This paper proposes a wideband ΔΣ fractional-N frequency synthesizer for software-defined radio application. The frequency synthesizer has two modes: the regular mode and the low-power mode. The regular mode and the low-power mode are selected to generate lower band frequency output for low-power applications and low band frequency signal with lower phase noise performance, respectively. The frequency...
A fractional-N PLL for multi-standard transceiver is presented. The tuning range covers dual bands of 0.38∼6GHz and 9~12GHz. A high-speed ultra-band divide-by-2 circuit is designed to accomplish the frequency band of 0.3 to 13.7GHz. A novel high isolation multiplexer is presented to achieve the frequency band selection in LO paths. This chip was implemented with 65nm CMOS technology and the maximum...
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