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An all-digital delay-locked loop (DLL) is presented in this paper. A new variable-step LPF state machine and a variable taps delay line are used here to achieve shorter lock in time than classical digital DLLs. The design is implemented in 0.18 mum CMOS technology. The experiment results show that the all-digital DLL can run at the frequency of about 800 MHz. The power dissipation of the DLL core...
A new level shifter used in multiple voltage digital circuits is presented. It combines the merit of conventional level shifter and single supply level shifter, which can shifter any voltage level signal to a desired higher level with low leakage current. The circuits was designed in 180nm CMOS technology and simulated in SPICE. The simulation results showed that the proposed level shifter circuit...
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