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This paper presents a technique that utilizes comparator timing information to accelerate successive approximation register (SAR) analog-to-digital converter (ADC) conversion process. With the scaling down of power supply voltage, the comparator delay is exponentially increasing. Thus, more information can be potentially extracted from the comparator transient response. In the proposed approach, the...
This paper presents a novel time and voltage based technique for successive approximation register (SAR) analog-to-digital converter (ADC) to improve the conversion speed. By taking advantage of the fact that at low supply voltage there will be a significant difference in comparator decision time for different input voltages, the proposed technique creates multiple auxiliary voltage levels for comparison...
The effective throughput of multiple-input–single-output (MISO) systems communicating over both independent and identically distributed (i.i.d.) and independent and nonidentically distributed (i.n.i.d.) – fading channels is investigated under delay constraints. New analytical expressions are derived for the exact effective throughput of both channels. Moreover, we present tractable closed-form...
Voltage comparators have been widely used in low-power sensor wake-up circuits for extracting digital bits from the envelope of received RF signals. This paper presents an alternative circuit to such comparators. The proposed circuit extracts digital bits by detecting the falling edge of the envelope signal. Since it essentially compares the values of the same signal at different times, it is potentially...
In this paper, we analytically investigate the achievable rate of multiple-input single-output (MISO) channels in the presence of delay constraints. In particular, we focus on the so-called effective rate which was recently established as a suitable metric for assessing the impact of delay constraints on the overall performance of communication systems. Yet, most prior relevant works have considered...
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