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Current paper proposes a system for identifying bearing faults of a 3-phase induction motor operated in process control application along with the presence of other source of vibration, in the same process. Different types of bearing fault identification techniques have been discussed in literature with the analysis of time domain, frequency domain and time-frequency domain based features. The proposed...
The present work, propose a system for vibration signal analysis of 3-phase induction motor when controlled by Variable Frequency Drive (VFD), in process control operation. The motors used in process control operation are subjected to dynamic speed along with load variations, thus most often fault occurs in rotating elements such as bearing. In literature, various bearing fault identification technique...
The idea of the test chip experiments started in ITC 1991 (McCluskey and Tseng, 2000). We wanted to get actual tester data that would answer some questions about manufacturing test of digital ICs. The objective was to find out the relative effectiveness of different test techniques, such as stuck fault tests, delay tests, IDDq, etc. The test chips are Murphy, ELF35, ELF18, and ELF13.
This paper presents a unique fault diagnostic to detect voltage unbalance in a three phase noisy power system. This has been achieved by continuously adding the three phase voltages resulting in a residual voltage. This voltage has been transferred to the frequency domain using DFT algorithm through which the fundamental residual voltage phasor is obtained. Training data have been generated through...
X-compactor is an X-tolerant test response compactor that is useful for massive reduction of test data volume and test time. This paper presents a technique for identifying failing flip-flops during scan test directly from the compacted response obtained from X-compactor outputs. The identified failing flip-flops can be used for several purposes - as inputs to a scan-based diagnosis tool to diagnose...
A gate exhaustive test set applies all possible input combinations to each gate in a combinational circuit, and observes the gate response at an observation point such as a primary output or a scan cell. In this paper, we analyze the effectiveness of the gate exhaustive test metric in detecting defective chips, and compare it with the single stuck-at fault, the N-detect, and the transition fault test...
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