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This paper highlights the successful co-integration of Localized Silicon-On-Insulator (LSOI) devices and of bulk-Si I/O devices on the same chip. LSOI devices present good logic performances and very low mismatch values down to 1.2mV/μm. In addition, we show the backbiasing impact on LSOI SRAM bit-cells for stability improvement. This work also presents the co-integration of LSOI with bulk devices...
The authors explored some of the challenges of the extremely thin SOI technology for mainstream CMOS. Faceted RSD was used to minimize parasitic capacitance. PFET performance is competitive with best bulk CMOS technologies, while NFET performance can be increased by further reduction in the series resistance. The impact of silicon thickness on the device variability was studied to quantify wafer uniformity...
The objective of this paper is to present the successful co-integration of Logic Ultra-Thin Body and Box (UTBB) devices and bulk-Si I/O devices on the same chip. The UTBB transistors are integrated locally on a Bulk wafer with the Localized Silicon On Insulator (LSOI) process technology with HfO2/TiN gate stack for low power applications. I/O co-integrated Bulk devices have a thicker interfacial SiO...
We present a new ETSOI CMOS integration scheme. The new process flow incorporates all benefits from our previous unipolar work. Only a single mask level is required to form raised source/drain (RSD) and extensions for both NFET and PFET. Another new feature of this work is the incorporation of two strain techniques to boost performance, (1) Si:C RSD for NFET and SiGe RSD for PFET, and (2) enhanced...
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