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In this paper, a 5-level hybrid converter is proposed. The circuit structure and the working principle are illustrated. The circuit is capable of providing five different voltage levels at the inductor input with the help of two flying capacitors. By reducing the voltage difference at the inductor input, the 5-level buck converter can use smaller inductors as compared to both 3-level and conventional...
This paper presents a variation tolerant driving technique for all-digital self-timed 3-level signaling high-speed SerDes transceivers. The proposed design generates the 3-level signal without a ½VDD driver, thus removing all the overhead and hassle of an additional supply. Moreover, the proposed all-digital scheme uses half the clock frequency while maintaining the same data rate of the conventional...
This paper proposes a new architecture that multiplexes both data and clock on serial links, reduces Inter symbol interference (ISI) by using a resistive termination technique, and uses two-level Manchester encoding to solve the reduced swing problem and enable the use of power efficient circuitry. Using this signaling scheme makes the system insensitive to jitter accumulation along the transmission...
Battery lifetime is one of the most important design considerations in rechargeable battery operated devices. Understanding the battery non-linear properties is essential for appropriate battery modeling. A new hybrid battery model is introduced which combines the battery electric circuit characteristics together with the non-linear battery properties.
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