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The Internet of Things (IoT) constrained devices show the urgent need for low power data security hardware cores. This paper presents a power efficient AES Core fabricated in UMC 130 nm CMOS technology by using Faraday standard cells library. The maximum throughput of the proposed AES Core is up to 2.6 Gb/s consuming about 0.2148 mW/MHz at 1.2V. The Dynamic Voltage and Frequency Scaling (DVFS) technique...
Internet of Things (IoT) devices are always having low power budget and high security demands. This paper describes the design and results of fabricated Advanced Encryption Standard (AES) chip in UMC 130 nm CMOS technology by using Faraday standard cells. The AES core is designed in fully QDI asynchronous circuit style. The core ciphers 128-bit data/key in 300 ns and consumes 5.47 mW.
This paper presents a new low power Current Conveyor II (CCII). The proposed circuit uses a 0.4 V single-ended supply. The advantages of the proposed current mode readout circuit are threefold. Firstly, the proposed circuit provides extremely low power consumption while operating all MOSFETs in the subthreshold region providing the highest energy efficiency. Secondly, Self cascode technique is used...
In this paper, the impact of thermal effects on low-power repeater insertion methodology is studied. An analytical methodology for thermal-aware repeater insertion that includes the electrothermal coupling between power, delay, and temperature is presented, and simulation results with global interconnect repeaters are discussed for 90nm and 65nm technology. Simulation results show that the proposed...
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