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This work investigates power losses in conventional and multi-level buck converters. Conduction and switching losses are modeled for conventional, 3-level and 5-level buck converters as a function of technology parameters, design variables and the operating point. It is shown that for a given set of technology parameters and optimized design variables, multi-level buck converters achieve higher efficiencies...
Dimensional analysis is one of the most powerful modeling methods, where it is used to reduce the number of physical variables through combining two or more variables into a single dimension neutral one in order to simplify the process of describing a relationship among those variables. That makes curve fitting to obtain final equations simpler. In this paper, dimensional analysis is applied as a...
Modeling parasitic parameters of Through-Silicon Via (TSV) structures is essential in exploring electrical characteristics such as delay and signal integrity (SI) of circuits and interconnections in three-dimensional (3D) Integrated Circuits (ICs). This paper presents a complete set of self-consistent equations including self and coupling terms for capacitance of general multi-TSV structures. The...
In this paper, a lumped element model for a through silicon via (TSV) is proposed based on the TSV physics. The proposed model is compact and compatible with SPICE simulators, hence it allows fast investigation of the TSV impact on 3-D circuits' performance. Exploiting this attractive feature of the proposed model, it is shown that the TSV has a negligible effect on high-impedance device characteristics,...
Modeling parasitic parameters of Through-Silicon Via (TSV) structures is essential in exploring electrical characteristics such as delay and signal integrity (SI) of circuits and interconnections in three-dimensional (3-D) Integrated Circuits (ICs). This paper presents a complete set of selfconsistent equations including self and coupling terms for capacitance of general multi-TSV structures. The...
A wide-band lumped element model for a through silicon via (TSV) is proposed based on electromagnetic simulations. Closed form expressions for the TSV parasitics based on the dimensional analysis method are introduced. The proposed model enables direct extraction of the TSV resistance, self-inductance, oxide capacitance, and parasitic elements due to the finite substrate resistivity. The model's compactness...
According to the International Technology Roadmap for Semiconductors (ITRS), the traditional scaling will no longer meet the performance and integration requirements of systems-on-chip (SoC) in the long term. Therefore, new I/O and packaging paradigms are needed. Three-dimensional integration is a promising alternative option to traditional 2D planar chips. 3D integration is mainly restricted by the...
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