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We demonstrate the chip-based 3D heterogeneous integration technology for realizing highly parallel 3D-stacked image sensor. Three kinds of chips, CMOS image sensor chip, analog circuit chip, and ADC array chip, which were fabricated by different technologies, are processed and stacked vertically to form a prototype 3D-stacked image sensor. Through-Si vias (TSVs) and metal micro-bumps are formed in...
In this paper, we describe the fundamental study of the block-parallel analog signal processing elements which includes CMOS image sensor, correlated double sampling (CDS) array, and analog-to-digital converter (ADC) array. To realize high-speed image capturing sensor, we have proposed a blockparallel signal processing with three-dimensional (3-D) structure. In proposed system, one block consists...
In this paper, we describe the fundamental study of a parallel signal processing circuit, which includes a pixel circuit and a parallel analog-to-digital converter (ADC) with hierarchical correlated double sampling (CDS). To realize high speed image capturing sensor, we have proposed a block-parallel signal processing with three-dimensional (3D) structure. Using 3D structure, the different function...
A three-dimensional (3-D) integration technology based on the wafer-to-wafer bonding using through silicon vias (TSV's) has been developed for the fabrication of new 3-D LSIs. A 3-D image sensor chip, 3-D shared memory chip, 3-D artificial retina chip and 3-D microprocessor test chip have been fabricated by using this technology. In addition, we have proposed a new reconfigurable parallel image processing...
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