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In this paper, a mechanism using drain-floated new MOS capacitor (NCAP) is proposed to improve the erase efficiency for the single poly embedded Flash memory. By floating the source/drain junctions of PMOS and new NCAP, we observe significant increase of the gate current in negative polarity, as the generated holes cannot diffuse out but accumulated in the channel region. This feature can be used...
A multitime programmable (MTP) memory cell based on pseudo differential architecture is presented in this paper. The proposed cell has only one floating gate, it takes advantage of the opposite polarity of PMOS transistor and NMOS transistor to output differential reading currents. The new cell has the same data retention capability as the state-of-the-art differential cell. Furthermore, it saves...
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