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40-Gb/s clock and data recovery (CDR) circuit with an integrated high-precision eye-opening monitor (EOM) circuit and an adaptive control scheme for optimizing the data decision point are presented. An adaptive decision-point control (ADPC) scheme using the EOM feedback overcomes the time-varying waveform distortion due to transmission impairment, which causes severe degradation of bit-error-rate...
We demonstrated an ultra-low jitter clock and data recovery (CDR) circuit that covers an ultra wide frequency range from 35 Gb/s to 46 Gb/s. Our CDR has a newly developed dual input LC-VCO with a fine/coarse tuning scheme and a dual-loop architecture, which consists of a phase tracking loop and a frequency tracking loop. The CDR chip, which was made using an InP-HBT process, shows an extremely clear...
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