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A fully integrated low-dropout (LDO) regulator with fast transient response is proposed in this paper. The capacitor-less LDO (CL-LDO) regulator incorporates both assisted pass-transistors and control circuit to realize adaptive transient current distribution during the load current transition, thereby enhancing the transient response and minimizing the output voltage's spike. In 65-nm CMOS process,...
Through the review and analysis of traditional and some recently reported conversion methods in SAR A/D converters, high speed, high resolution and low power approaches for SAR A/D converter are discussed. Based on SMIC 65 nm CMOS technology, two typical low power methods reported in previous works are validated by circuit design and simulation. Design challenges and considerations of high speed SAR...
A 10-bit 3 Ms/s 90 nm CMOS SAR A/D converter is presented in this paper. Pseudo-differential comparison architecture is utilized to improve the performance, where the errors caused by clock feed-through and charge injection can be considered as common-mode interferences. Instead of traditional voltage scaling architecture, an R-C combination based D/A converter is used to reduce the chip area. And...
Through the research on charge redistribution SAR A/D converter, three energy-efficient capacitor arrays are discussed in this paper. The switching energy of the traditional architecture, charge sharing architecture, capacitor splitting architecture and two-step architecture capacitor arrays is derived and analyzed. Based on SMIC 65 nm CMOS process, 10-bit SAR A/D converters of all these architectures...
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