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An at-speed self-testable technique is proposed for the high speed domino adder. We apply pseudo-exhaustive testing so that all testable faults in the 64-bit adder are detected by just 23K patterns. The adder latency is accurately measured by the programmable-skew clock generated from delay-locked loop (DLL). The proposed technique is validated on a 6.4GHz 64-bit domino adder with 181ps latency in...
A novel 64-bit hybrid radix-4 sparse-4 tree adder using clock-delayed (CD) footless domino logic is proposed. The adder operates at 6.4GHz with 181ps latency and it consumes 840mW at 1.2V in a standard 90nm CMOS technology. The adder latency is accurately measured by the programmable clock generated from delay-locked loop (DLL). Pseudo-exhaustive testing is applied so that all testable faults in this...
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