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Due to the coexistence of different generations of mobile radio technologies, more and more mobile network operators are keen on deploying multiple radio technologies on a single cell site and carry their traffic over a common transport network. This paper studies such a collocated multiradio system: collocated LTE and HSDPA. Firstly, we investigate the potential gain by using a shared transport network...
This paper presents a novel diagnosis algorithm for small delay defects (SDD). Faster-than-at-speed test sets are generated by masking long paths in the circuit for testing SDD. The proposed diagnosis technique uses timing upper and lower bound to improve the diagnosis resolution. Also, timing-aware single location at a time (TA-SLAT) technique is proposed to diagnose multiple SDD. Test results of...
A systematic flow is described for characterizing, modeling, and simulating single event transient-induced soft errors in cell-based designs. Pulse broadening effects are quantified for a 65 nm CMOS process.
We investigate two different node structures with fiber delay lines (FDLs) in optical burst switching networks: FDL share per node and FDL share per link. We study the roles of maximum delay and the single FDL element granularity in FDL share per node. Our simulations show that FDLs with limited delay can effectively improve the network performance in terms of burst loss probability, but increasing...
On-chip interconnect structures become much more complicated and dominate system performance in multi-core SoCs. Oscillation ring test is an efficient test method for most types of faults in the interconnect structures, and previous studies show that a 100% fault coverage and good diagnosis resolution for various fault models is achievable. The test time of oscillation ring test is decided by the...
This poster presents very-low-voltage (VLV) testing for digital NMOS circuits based on amorphous silicon thin-film (a-Si TFT) transistor technology as an economic alternative to burn-in. A total number of 140 CUT implemented in 8??m a-Si TFT technology are tested at nominal voltage and very-low-voltage. The results indicate that VLV testing is effective in screening out unreliable a-Si TFT circuits.
This paper presents very-low-voltage (VLV) testing for digital NMOS circuits based on amorphous silicon thin film transistor (a-Si TFT) technology. The proposed VLV testing is an economic alternative to burn-in because the former is non-destructive and can be easily performed on regular ATE in a short time. 140 circuits under test (CUT) of two different design styles are implemented in 8 mm a-Si TFT...
Power consumption is an important issue in nanoscale circuits. The multiple supply voltages (MSV) technique, where non-critical parts are supplied with the lower supply voltage, can be used to balance power and performance, as both dynamic and leakage power are reduced with the lower supply voltage. However, level converting circuits must be inserted between different voltage domains to avoid leakage...
The voltage islands scheme using multiple supply voltages (MSV) has been widely used in system-on-chip (SoC) designs to reduce the unnecessary power dissipation in non-critical function blocks. In these SoC designs, the circuit blocks with the same voltage level are clustered into a single voltage island to reduce the cost of voltage supply network and the power consumption. However, a voltage level...
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