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The proliferation of multiple WLANs and the continuous scaling of CMOS have created the need for low-voltage multistandard WLAN receivers. Instead of approaching a complicated SoC, a 3D-stack SiP appears as a promising alternative to meet those requirements in conjunction with the obvious goals of low power and low cost. This paper, focused on the SiP implementation of a WLAN receiver, presents the...
Presented is a low-voltage low-power analog-baseband IC featuring a two-step channel-selection architecture for a flexible-IF reception of 802.11a/b/g. In circuits, it integrates innovatively series-switching mixers for a precise I/Q demodulation; an inside-opamp dc-offset cancellation for area savings and switchability, a switched-current-resistor programmable-gain amplifier for a transient-free...
Multistandard-compliant wireless transceivers with low-voltage low-power implementation are in great demand to match the proliferation of multiple WLANs and the continuous scaling of CMOS technologies. This paper proposes both the architecture and the corresponding circuit techniques to implement a low-IF/zero-IF reconfigurable receiver IF-to-baseband chip for IEEE 802.11a/b/g WLAN. Optimum low-voltage...
Two circuit techniques, namely switched-current-resistor (SCR) and switchable DC-offset canceler (S-OC) inside opamp, are proposed to realize a low-voltage, transient-free and constant-bandwidth programmable-gain amplifier (PGA) with also adaptive stage-DC-offset cancellation. Fabricated in 0.35-mum CMOS, the PGA dissipates 7.4mW from 1V. The mean and standard deviation of the bandwidth over 52-dB...
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