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Wafer level packaging (WLP) is regarded as one of the most potential single chip packages for its compatibility with wafer fabrication process. As the pitch size of the package becomes lower, the reliability of fine pitch WLP devices is greatly challenged. Finer pitch may result in weaker solder joints, which leads to reliability problems such as fatigue failure, creep deformation and so on. Much...
Micro copper pillar bumps (μCPBs) have been an important electrical interconnect method for fine pitch I/O applications such as 2.5D IC integration. The thermal stress induced by the coefficient of thermal expansion (CTE) mismatch between a Cu/low-k silicon die, micro copper pillar bump and through silicon via (TSV) based silicon interposer is a significant reliability issue for 2.5D IC integration...
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