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This paper briefly presents a 60-GHz dual-chip wireless communication solution adhering to the IEEE 802.11ad standards. The proposed fully-integrated transceiver front-end chip (RFIC) using a sub-harmonic sliding-IF scheme to reduce the design difficulty on VCO, was implemented based on a low cost SiGe 0.18um BiCMOS process and has a compact chip area of 5mm by 3.9mm with a low power consumption of...
Higher loss of commercial silicon substrate, which has the substrate resistivity of about 10Ω • Cm, is always a headache for the IC designer. We proposed a generalized multiple coupled tanks topology, which can reduce the substrate loss and enhance the circuit performance. The general concept, analysis and circuit examples are presented in this paper for the demonstration and verification.
With recent technique advancement, CMOS silicon-on-insulator (SOI) technology seems to be attractive for the implementation of the RF, Microwave and millimeter-wave circuits and systems due to its excellent feature of lower loss, lower noise and good power handling capabilities as compared to its CMOS counterpart. This paper is going to study the state of the art CMOS SOI processes and the applications...
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