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This paper investigates the various aspects of network on Chip(NoC) design and its FPGA implementation. A parametric approach of evaluating the FPGA resources, delay and maximum frequency of operation for a NoC design has been described which may help the designer to take early decision related to NoC designing and prototyping. Virtual channel(VC), flit buffer depth and flit data width are taken as...
Direct Digital Synthesizers (DDSs) or Numerically Controlled Oscillators (NCOs) are nowadays prominently used in the applications of RF signal processing, satellite communications, etc. This paper brings out the FPGA implementation of one such DDS which has quadrature outputs. The proposed design, which is based on pipelined CORDIC, has considerable improvement in terms of spurious free dynamic range...
This paper presents architecture of CORDIC, embedded with a scaling unit that has only minimal number of adders and shifters. It can be implemented in rotation mode as well as vectoring mode. The purpose of the design is to get a scaling free CORDIC unit preserving the design of original algorithm. The proposed design has a considerable reduction in hardware when compared with other scaling free architectures...
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