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This paper proposes a systematic sizing methodology for switched-capacitor DC/DC converters aimed at maximizing the converter efficiency under the die area constraint. To do so, we propose first an analytical solution of the optimum switching frequency to maximize the converter efficiency. When the parasitic capacitances are low, this solution leads to an identical contribution of the switches and...
Ultra-low-voltage processors of highly duty-cycled applications such as wireless sensor nodes must support two modes of operation: active mode and sleep mode. Even in sleep mode some critical blocks such as retentive SRAM, timer and interrupt controller must remain powered-on. The DC/DC converter thus need to be able to supply ultra-low loads corresponding to sleep mode. In this paper, we propose...
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