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A low power all-digital phase locked-loop (ADPLL) in a 0.13um CMOS process is presented. The pulse-based digitally controlled oscillator (PB-DCO) performs a high resolution and wide range. The locking time of ADPLL is less then 32 reference clock cycles. The multiplication factor is 2 to 63. Power consumption is 260uW at 160-MHz and 80uW at 60-MHz with 0.5V supply voltage.
A 150-450-MHz, all-digital phase locked-loop (ADPLL) in a 0.1 um CMOS process is presented. The pulse- based digitally controlled oscillator (PB-DCO) performs a high resolution and wide range. The bulk-controlled varactor minimizes jitter performance. The worst case for frequency acquisition is 32 reference clock cycles. The multiplication factor is 2-63. The rms and peak-to-peak jitters are 6.7 ps...
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