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An Integrated Power Board technology was used to construct a 3D power module. This packaging is suitable for use of WBG devices as it reduces the inductive parasitics to the strict minimum, with a 2nH loop inductance in our 1.2kV/80A SiC prototype using SiC MOSFETs. The packaging presents virtually no parasitics or necessity for slowing down the commutation, which is oscillation-free. The conducted...
A new three dimensional package based on Printed Circuit Board (PCB) embedded die technology is presented in this paper. The package takes advantage of the Power Chip On Chip (PCOC) concept, where commutation cell is housed within the bus bar, allowing a very low inductance design for the package of up to 0.25 nH. Two key design challenges with the package relate to the layout and the thermal management...
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