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A 5-bit flash ADC incorporates 20 mum by 20 mum inductors to improve both comparator preamplification bandwidth and regeneration speed. A switched-cascode scheme reduces comparator kickback. Offset cancellation is achieved by modifying the comparator reference voltages without degrading high-speed performance. The ADC achieves a measured SNDR of 27.5 dB for a 5 MHz input at 4 GS/s, and 23.6 dB for...
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