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FRC (frame re-compression) is a kind of widely used technique in reducing the SDRAM (synchronous dynamic random access memory) bandwidth of HEVC video system. However, in previous research works, FRC imposes requirements on accessing pattern and hence its usage are only limited in HEVC video codecs. While in a typical HEVC VLSI video system, there exists many other video IPs with high bandwidth requirements...
A demonstration of FPGA-based 3840×2160 UHDTV (Ultra-high definition TV) H.264 video decoding and displaying system is proposed in this paper. The proposed system can decode and display 3840×2160 video by two Altera Stratix III DE3 FPGA boards, which are connected together with each other by HSTC cable. Video processing system requires high memory bandwidth. This paper locate decoder module and display...
In the latest draft video compression standard, HEVC, a new 8-tap MC interpolation filter is adopted. For this component, we propose an efficient VLSI design which is composed of a reconfigurable filter, an optimized pipeline engine organization, and a filter reuse scheme. This results in 30% area saving from a non-optimized design. The proposed implementation supports a maximal throughput of QFHD@60fps...
This paper proposes a high-performance intra prediction architecture that can support H.264/AVC high profile. The proposed MB/block co-reordering can avoid data dependency and improve pipeline utilization. Therefore, the timing constraint of real-time 4k×2k encoding can be achieved with negligible quality loss. 16×16 prediction engine and 8×8 prediction engine work parallel for prediction and coefficients...
This paper presents a new architecture for high performance intra prediction in H.264/AVC video coding standard. Our goal is to design an intra prediction engine for 4K??2K@60fps ultra high definition (UHD) decoder. The proposed architecture can provide very stable throughput, which can process any H.264 intra prediction modes within 66 cycles. Compared with previous design, this feature can guarantee...
This paper presents a new architecture for high performance intra prediction in H.264/AVC video coding standard, which can support H.264 high profile features. Our goal is to design an Intra prediction engine for Ultra High Definition (UHD) Decoder (4 K x 2 K @ 60 fps). The proposed architecture can achieve very stable throughput, which can process any H.264 intra prediction modes within 66 cycles...
This paper presents a VLSI architecture of CABAC decoder for H.264/AVC level 5.1 applications. It adopts a symbol-prediction-based decision engine with extra-bypass decoding support, a four-stage bypass engine, along with dedicated arithmetic decoding modes to increase the throughput rate. It also reduces the context model access time significantly by applying context pre-fetch register set. The proposed...
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