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In recent, with the nanometer-scale size, high density, and high frequency of VLSI, the reliability of VLSI is declined by the small-delay defects which are hard to be detected by traditional delay fault testing. As a method for detecting small-delay faults, on-chip delay measurement was proposed, which measures the delay time of paths on Circuit Under Test (CUT). However, if the Path Under Measurement...
In recent high-density and low-power VLSIs, soft errors occurring on not only memory systems and the latches of logic circuits but also the combinational parts of logic circuits seriously affect the operation of systems. The conventional soft error tolerant methods for soft errors on the combinational parts do not provide enough high soft error tolerant capability with small performance penalty. This...
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