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GAA nanowires (NW) transistors are promising candidates for sub 10 nm technology nodes. They offer optimal electrostatic control, thereby enabling ultimate CMOS device scaling. Horizontally stacked they are a natural extension of today's mainstream technology. Considering enlarged NWs in Nanosheets (NS) allows to target the best compromise in power and performance for future applications. In this...
A lot of works have been done to propose and study alternative devices for future electronics. Between the possible candidates (Tunneling FETs, stacked nanowires…), Reconfigurable FET (RFET) appears as an interesting option to achieve reprogrammable logic in future circuits. The first step to evaluate the potentialities of new devices at circuit level is compact modeling. For the first time we propose...
In this paper we develop a compact model for ballistic/quasi-ballistic transport in nanowire. Starting from the well-known approach of Natori/Lundstrom, we enhanced it by including an original modeling of SCE/DIBL (Short Channel Effect and Drain Barrier Lowering), scattering mechanisms and quantum mechanical confinement. Our drain current model has been validated by comparisons with numerical simulations...
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