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A 4.8GHz CMOS LC VCO with 37.5% tuning range in 0.5-V supply is presented. The VCO achieves low power consumption by optimum selection of inductance in the L-C tank. To increase the tuning range, a three-bit switching capacitor array is used for the digital switched tuning. A voltage-boosted technique is used to generate a high voltage for the switches in the digital tuning scheme. Designed in 0.13μm...
This study was initiated to design a low noise amplifier (LNA), which could work with ultra low voltage of 0.5V and was optimized for WSN application using SMIC 0.13 μm RF-CMOS technology. The topology of differential inductance degenerated folded cascode based on power-constrained simultaneous noise and input matching (PCSNIM) technique was adopted. Chosen circuit demonstrated a power gain of 16...
Low supply digital blocks for OC-768/STM-256 optical communication systems such as 1:2 demultiplexer (DEMUX), 2:1 multiplexer (MUX), 2:1 frequency divider and data decision circuit in 0.13 mum CMOS are presented. All proposed blocks are based on fully differential MOS current-mode logic (CML). Multi-stage output buffers are used to drive the external 50 Omega loads. On-chip shunt peaking (SP) inductors...
This paper presents the design of the matching network of a 60-GHz high-gain LNA. Through analyzing commonly used structure, a simplified input matching network was designed and an inter-stage matching network was proposed to improve gain and reduce noise. Simulated in 0.13-μm SiGe BiCMOS technology, the LNA provides a gain of 20 dB with a noise figure of 5 dB while consuming 3 mA from a 2.5-V supply.
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