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In this paper, a framework for the statistical design of the flip-flops circuits is proposed to achieve a high yield, while meeting the performance, leakage power, switching power, and layout area design specifications. The proposed design solution provides the nominal design parameters, i.e., the widths and lengths of the flip-flop transistors, which provide maximum immunity to the process variations...
In low power synchronous systems, sub-threshold flip-flops are used to reduce the total power dissipation. Moreover, process variations create a large variability in the flip-flop power in scaled technologies impacting the power yield, especially, for sub-threshold operation. This paper presents an analysis of power yield improvement of four commonly used flip-flops under process variations. These...
This paper presents a statistical framework for the design of flip-flops under process variations in order to maximize their timing yield. In nanometer CMOS technologies, process variations significantly impact the timing performance of sequential circuits which may eventually cause their malfunction. Therefore, developing a framework for designing such circuits is inevitable. Our framework generates...
Due to CMOS technology scaling, devices are getting smaller, faster, and operating at lower supply voltages. The reduced capacitances and power supply voltages and the increased chip density to perform more functionality result in increasing the soft errors and making them one of the essential design constraints at the same level as delay and power. Even though the impact of process variations on...
In deeply pipelined synchronous systems, any violation of the timing constraints of the flip-flops can cause the overall system to malfunction. Due to CMOS technology scaling, increased process variations result in a large delay variability causing unacceptable loss in the timing yield. Several variation tolerant techniques are introduced to mitigate this variability challenge by improving the timing...
In synchronous systems, any violation of the timing constraints of the flip-flops can cause the overall system to malfunction. Moreover, the process variations create a large variability in the flip-flop delay in scaled technologies impacting the timing yield. Overtime, many gate sizing algorithms have been introduced to improve the timing yield. This paper presents an analysis of timing yield improvement...
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