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This work proposes a chaotically injected timing technique (CITT) for ring-based oscillators. The quality of clock signal affects the normal motion of the entire circuit. In many oscillators and clock generators show the performance comparison through jitters and phase noise. The injection-locked ring-based oscillators have advantages of jitters, phase noise and area cost. However, there is a contingent...
This paper proposes an ultra-low-voltage all-digital phase-locked loop (ADPLL) with a digital supply regulator (DSR). The DSR maintains an RMS jitter for a 280-MHz output signal of less than 0.55% when a 100-kHz to 100-MHz supply noise is produced on a digitally controlled oscillator (DCO). The DCO uses the two-step timing resolution of a digitally controlled varactor to achieve the high timing resolution...
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