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This paper presents a low-power and compact passive supply-resonance (SR) suppression filter. By using an on-chip waveform monitor, a power-delivery network (PDN) impedance including package, and board PDNs is in-situ analyzed to identify the SR frequency fSR. A notch filter which consists of coupled bonding-wire coils and an on-chip MOS capacitor bank is auto-tuned for the SR suppression. This passive...
Direct RF power injection on a power delivery network causes timing variations of inverter chains. The amount of period jitter in an inverter chain is strongly dominated by the frequency and amplitude of sinusoidal voltage variations on its internal power supply nodes. The conduction and conversion characteristics of the RF power from an external point of injection to the sinusoidal voltage variation...
In this paper, the susceptibility of a CMOS bandgap voltage reference (BGR) to external noise was investigated using an on-chip waveform monitor circuit in conjunction with circuit simulations. A Direct RF Power Injection method was employed for the immunity test of the BGR. Also, we evaluated the performance of the on-chip waveform monitor and analyze the BGR immunity using the on-chip monitor. As...
This paper presents the measurements of power noise (Vdd noise) waveforms of a 5-stage inverter chain, using on-chip noise monitor circuits (OCM). The fine resolution of 0.4 mV in voltage and 12.5 ps in timing are realized. The undesired voltage variation by signal buffers in I/O cells is carefully eliminated by three means; (i) isolation of power domains, (ii) subtraction of background noise waveforms,...
An effective supply voltage monitor evaluates dynamic variation of (Vdd-Vss within power rails of integrated circuits on a die. The monitor occupies an area of as small as 10.8 × 14.5 μm2 and is followed by backend digitizing circuits, both using 3.3 V thick oxide transistors in a 65 nm CMOS technology for covering all power domains from core circuits to peripheral I/O rings. A prototype demonstrates...
SRAM exhibits the sensitivity of false operation against static and sinusoidal supply voltage variation. A measurement system combines direct radio frequency (RF) power injection, on-chip monitoring of voltage variation on power supply lines, and built-in self test of memory read/write operations. The bit error rate (BER) of an SRAM core exponentially increases when the lowest instantaneous voltage...
Power noise could decisively impact on the system performance of large-scale integration (LSI), with higher integration and lower power supply voltage. Power noise simulation becomes a key step in the design of LSI systems. This paper presents an original capacitor-charging model that expresses AC part of power consumption current and also demonstrates power noise simulation of a 32 bit microprocessor...
On-chip and on-board power noise measurements were performed on a 32-bit microprocessor core in a 90-nm CMOS technology. The on-chip voltage noise and on-board near-field magnetic field measurements are related to each other with a unified power delivery network that is formed by on-chip and on-board parasitic components. The significant importance of LSI chip-package-board co-simulation is also discussed...
Performance of soft magnetic CoZrNb film as a thin film noise suppressor and its application to an noise emulator chip fabricated by 90/65nm CMOS technology are discussed. Intra-chip decoupling was studied by the electromagnetic coupling between two miniature coils made on a noise test chip implemented in CMOS 90nm technology. Inter-chip decoupling (radiation) was evaluated by the coupling between...
A direct power injection (DPI) method evaluates the immunity of a static random access memory (SRAM) core in a 90 nm CMOS technology, with on-die diagnosis structures of memory built-in self test (MBIST) and on-chip voltage waveform monitoring (OCM). The magnitude of sinusoidal voltage variation introduced by DPI is quantified by OCM. The number of resultant erroneous bits as well as their distribution...
Power noise of an integrated circuit (IC) chip is dominantly characterized by the frequency-domain impedance of a chip-package-board integrated power delivery network (PDN) and the operating frequency of circuits. A 65 nm CMOS chip embedding a high precision on-chip waveform capture clearly exhibits the relation of AC power noise components with the parallel resonance seen from on-chip digital circuits...
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