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Two novel ESD power clamp design techniques for SOI FinFET CMOS technology are reported. First, a layout improvement technique is discussed for stacked gated diodes, which reduces the required area for a given ESD robustness and at the same time reduces the on-resistance of the clamp. Secondly, circuit design techniques are used to convert a standard RC-triggered active ESD clamp into a bi-directional...
A new design methodology for FinFET devices is presented, which takes into account all complex dependences on both layout and process parameters of the electrostatic discharge (ESD) electrical device parameters of NMOS FinFET devices operating in parasitic bipolar mode. This methodology allows optimization toward a given ESD target (area consumption, leakage current, voltage drop, parasitic capacitance,...
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